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Design Verification Engineer - UVM/SystemVerilog - Virtual Instruments

San Jose, CA, US


Job Site: San Jose, California (telecommuting from anywhere in the U.S. acceptable)



This position will work on the leading edge UVM/SystemVerilog methodologies developing key IP designs that provides solution for VI products including packet processing, high speed interprocess communication, low level functions and others.

Responsibilities

As a Design Verification Engineer and the Principal Member of Hardware Team, the ideal candidate would be responsible for the following:

Architect and Implement leading edge verification solutions.
Work closely with team members to understand the packet generation for Fibre Channel, Ethernet, TCP/IP, File and Block Protocols, develop verification plans and tests to verify complex features of the FPGA designs.
Execute the verification test plan by developing checkers, stimulus and coverage using UVM and System Verilog and running simulations.
Design & develop productivity through process/tool/methodology solutions and take steps towards reusable and maintainable code that can be used over multiple generations of company products.
Predict the scope of work and coordinate with all team across functional groups to set direction and establish priorities.

Requirements

At least 10 years of proven verification experience of complex projects.
Proven developer of complex verification checkers and stimulus using OVM/UVM or equivalent.
Extensive experience in functional modeling of industry/internal interfaces with SystemVerilog.
Excellent debug skills with ability to quickly and accurately root cause failures and make high quality verification fixes.
Experience writing and closing functional coverage on complex functions.
Masters/Bachelor degree with emphasis in Electrical Engineering, Computer architecture, or Computer Science.